Mixed-Signal Design Engineer, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
- 8 years of experience in analog mixed signal or high-speed IO development.
- Experience defining and taking to HVM leading edge mixed-signal or high-speed IO designs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on wireline silicon architecture and design.
- Experience working on high-performance, data-center class IP, from concept through high-volume deployment.
- Experience and technical innovation in mixed-signal and high-speed IO solutions.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you’ll work to shape the future of strategic data center silicon. Our portfolio spans CPU, TPU, Networking and other key data center technologies, which power Google's most demanding compute and AI/ML applications. You’ll be an early and key contributor in a nascent high-growth team that pushes boundaries, developing advanced custom IP and solutions.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Design of high-speed analog/digital circuits (e.g., ADC, DAC, PLL, CDR, DSP), including optimizing for Power, Performance, and Area (PPA).
- Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
- Bring up new silicon, characterize performance, and test for electrical compliance in lab environments.
- Work with packaging, board design, and firmware teams to ensure seamless integration into System-on-Chips (SoCs).
- Adhere to standards like IEEE or OIF for high-speed protocols and optimize power consumption.
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