Senior Design Verification Engineer, Networking, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).
- Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).
- Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in standard verification methodology.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Science.
- Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
About the job
As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
- Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
- Define and implement various coverage measures to capture stimulus and corner-case scenarios.
- Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
- Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.
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