Static Timing Analysis Manager, Full Chip, SOC, Implementation
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with silicon implementation and chip integration.
- Experience with STA sign-off constraint authoring for full-chip level, tapeout sign-off requirements, checklists, and associated automation.
- 3 years of experience in people management, developing employees.
- Experience delivering silicon.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends with the knowledge of semiconductor device physics and transistor characteristics.
- Experience in engineering across physical design, top-level implementation, GDS tape-out.
- Ability to deliver silicon in state-of-the-art technology process nodes.
- Ability to lead cross-functional teams.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Lead and manage functional STA team responsible for delivering system-on-chip (SoC) Static Timing Analysis.
- Execute full chip timing signoff checklist, perform full chip STA, power recovery, timing ECO creation and oversee final timing signoff for SoC’s.
- Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
- Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area.
- Collaborate with front-end, Design for Test (DFT) and Computer-aided design (CAD) teams for the design exploration and closure.
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